This invention relates to a one-shot signal generation circuit which generates a one-shot signal for determining the internal operational timing of an asynchronous memory.
As a conventional asynchronous memory, there has been a memory which operates by generating a one-shot signal internally when an external address has changed. As a one-shot signal generation circuit for generating this one-shot signal, generally a circuit as shown in FIG. 19 is employed. The one-shot signal generation circuit shown in this figure detects change (transition) of address signals A0-AX which are its input signals, generates a plurality of address transition detection signals (hereinafter termed ATD signals) in pulse form, and combines these ATD signals into a single one-shot signal. Various internal signals for providing timing for internal operations, such as latch signals for latching addresses, are generated from the one-shot signal which has been generated in this manner.
The structure of a one-shot signal generation circuit according to the background art will be explained in the following in concrete terms. In FIG. 19, the reference symbols 5-0 to 5-X denote address transition detection circuits (ATD0-ATDX). These address transition detection circuits 5-0 to 5-X detect transitions of address signals A0-AX, and generate ATD signals having pulse widths greater than the skew widths which these address signals A0-AX have. The reference symbol 6 denotes a NOR gate (a negative logical sum gate circuit). This NOR gate 6 combines the plurality of ATD signal output from the address transition detection circuits 5-0 to 5-X into a single signal S6 (a pulse signal).
The reference symbol 7 denotes a predetermined number (an odd number) of inverter gates connected together as a cascade, and the reference symbol 8 is a NOR gate. In this example, the inverter gates 7 and the NOR gate 8 constitute an edge detection circuit which detects the low edge of the output signal S6 of the NOR gate 6, and, when the low edge is input, a one-shot signal S8 is output which has a pulse width corresponding to the delay time of the inverter gates 7. These inverter gates 7 and the NOR gate 8 function as a timing adjustment circuit for adjusting the timing of the output signal of the NOR gate 6, and they adjust the pulse width of the one-shot signal which is output from the NOR gate 6 to a pulse width which corresponds to the delay time provided by the inverter gates 7.
According to this background art circuit structure, after the arriving address signals A0, A1 . . . , AX which have skew have been subjected by the address transition detection circuits (ATD0-ATDX) 5-0, 5-1 to 5-X to waveform shaping into ATD signals (the output signals of the address transition detection circuits 5-0 to 5-X) which have pulse widths greater than the skew widths of the address signals, these signals are combined by the NOR gate 6 into a single signal. Accordingly, the output signal of this NOR gate 6 has a pulse width greater than the skew widths of the address signals A0, A1-AX. The timing adjustment circuit which is made up from the inverter gates 7 and the NOR gate 8 adjusts the timing of the output signal of the NOR gate 6, and generates the one-shot signal S8 which has a predetermined pulse width.
FIG. 20 shows the address transition detection circuit (ATD0) 5-0. The structures of the other address transition detection circuits (ATD1-ATDX) 5-1 to 5-X are the same as that shown in FIG. 20.
In FIG. 20, the reference symbol 170 denotes a delay circuit, the reference symbol 171 denotes an inverter, and the reference symbols 173, 174, and 175 denote NAND gates (negative logical product gates). Here, along with the input signal (the address signal A0) being delayed by the delay circuit 170 and becoming one of the input signals to the NAND gate 173, also it is inverted by the inverter 171 and, in the same manner, becomes the other input signal to the NAND gate 173. The delay circuit 170, inverter 171, and NAND gate 173 constitute a circuit system which detects the fact that the input signal has undergone a transition from high level to low level.
Furthermore, along with the input signal (the address signal A0) being delayed by the delay circuit 170 and becoming one of the input signals to the NAND gate 174, also it becomes the other input signal to this NAND gate 173. This delay circuit 170 and NAND gate 174 constitute a circuit system which detects the fact that the input signal has undergone a transition from low level to high level. The NAND gate 175 combines the pulse signals output from the NAND gate 173 and the NAND gate 174 into a single signal. In this example, when the input signal has undergone a transition, one or the other of the NAND gate 173 and the NAND gate 174 outputs a pulse signal at low level, according to the direction of this transition. The NAND gate 175 receives these pulse signals and outputs the ATD signal. The pulse width of this ATD signal is determined by the delay time of the delay circuit 170.
For the delay circuit 170 which is used in the address transition detection circuit, there are the circuit type shown in FIG. 21 and the circuit type shown in FIG. 22. The circuit type of FIG. 21 is a delay circuit in which a plurality of inverter gates 180 are connected as a cascade, and it provides the desired delay time by accumulating the operational delay time of each of the inverters. Furthermore, the circuit type of FIG. 22 is a delay circuit in which a capacitor 191 is connected to each stage of inverter gates 190 which are connected as a cascade, and it provides the desired delay time by delaying the output signals of the respective inverters with the capacitors 191. The delay time of this delay circuit 170 is set to a value which is greater than the skew width of the address signal.
As has been explained above, according to the background art, since the pulse widths of the ATD signals which are respectively output from the address transition detection circuits 5-0, 5-1 to 5-X are greater than the skews of the address signals A0, A1-AX, the one-shot signal which is output from the NOR gate 8 is not separated into a plurality of pulse signals even due to the input of address signals A0, A1-AX which arrive having skew, but is generated as a single pulse signal.
However, with the address transition detection circuits according to the background art, problems occur like the following due to the use of various types of delay circuit such as the delay circuit 170 for determining the pulse width of the ATD signal and the inverter gates 7 for timing adjustment and so on.
(1) Increase of Current Consumption by the Delay Circuit
Among the circuit systems for the delay circuit 170 which makes up the address transition detection circuit, according to the circuit system shown in FIG. 21, a large number of inverter gates of high drive power connected in a cascade are required for each of a plurality of ATD signals (for each address transition detection circuit). Accordingly, with this circuit system, there are the problems that the occupancy area upon the chip becomes large, and moreover the power consumption is increased by the activation of the large number of inverter gates of high drive power.
(2) Variation in the Delay Time of the Delay Circuit
The circuit system shown in FIG. 22 is made by connecting inverter gates whose drive power is small in a cascade, and it generates its delay time by driving each of capacitors with each of the inverter gates. Here, variations in the drive power of the inverter gates come to exert a great influence upon the delay time when the number of stages of the inverter gates is increased, since the amounts of variation in the drive power of the inverter gates are superposed. Furthermore, the smaller are the transistors in gate width and gate length, the more does the accuracy of alignment of the mask for the manufacturing process greatly influence their electrical characteristics.
Due to this, when for example low drive power inverter gates are made using transistors which have small gate width, and a large number of stages of these inverter gates are connected together to form a delay circuit, by comparison to the case in which transistors of large drive power are used, variations in the drive power of the inverter gates (the current drive power of the transistors) come to exert a great influence upon the delay time (the charge and discharge time). Accordingly, with this circuit system, it becomes easy for the delay time of the inverter gates which are connected in a cascade to suffer the influence of production deviations, and the problem arises that it becomes difficult to obtain an accurate delay time.
(3) Breakup of the Pulse Signal Due to Skew of the Input Signal
When, due to variations in the current drive power of the transistors, the delay time of the delay circuit 170 which constitutes each of the address transition detection circuits varies so as to become shorter, it becomes impossible to combine the ATD signals which are output from the address transition detection circuits into a single pulse signal with the NOR gate 6, due to the amount of skew included in input signals, and it may happen that a plurality of pulse signals are output from the NOR gate 6. In this manner, when the pulse signal which is output from the NOR gate 6 is divided into a plurality thereof, it becomes impossible to generate a proper one-shot signal.
(4) Variation of the Pulse Width Due to Reduction of the Period of the Input Signal
With the structure shown in FIG. 19, if for example the period of the address signal A0 is short, the phenomenon occurs that the pulse width of the pulse signal which is output from the NOR gate 8 becomes narrower than the proper pulse width. With regard to this phenomenon, the case in which the address signal A0 changes over will be explained with reference to the waveform shown in FIG. 23 in concrete terms as an example.
First, the correct operation will be explained. Now, when the address signal A0 changes over at the time t1 shown in FIG. 23, the address transition detection circuit 5-0 detects this signal transition and outputs an ATD signal. The NOR gate 6 receives this ATD signal and outputs a signal S6. In other words, the signal S6 is changed over to low level in response to the change in the address signal A0, and after a fixed time it returns back to high level. The signal S8 which is output from the NOR gate 8 changes to high level upon receipt of the change in the signal S6. On the other hand, the signal S6 is delayed by the inverter gates 7 to become the signal S7, and the signal S7 changes to high level after a predetermined time from when the signal S6 changes. Due to this, the signal S8 which is output from the NOR gate 8 returns to low level. In summary, when the address signal A0 changes over, a signal S8 having a pulse width corresponding to the delay time of the inverter gates 7 is correctly generated.
Next, the operation (improper operation) in the case that the address signal A0 changes over at the time t2 shown in FIG. 23, and the address period Tadd has become short, will be explained.
In this case, in the same way as with the case described above, the signal S6 changes to low level upon receipt of the change of the address signal A0. Here, according to proper operation, as shown by the dotted line in FIG. 23, the signal S8 would change to high level in response to change of the signal S6. However, since in the previous cycle the low level of the signal S6 was delayed by the delay circuit 170 and is reflected in the signal level of the signal S7, even if the cycle changes over, the signal S7 is maintained at high level for a certain period. Due to this, the signal S8 does not respond to the signal S6, and comes to be at high level upon receipt of the signal S7. Accordingly, in this case, the rising slope of the pulse of the signal S8 is delayed, and the pulse width of the signal S8 becomes narrow. In this manner, according to the structure shown in FIG. 19, when the period of the address signal becomes short, the problem arises that the pulse width becomes narrow.
(5) Variation of the Pulse Width Due to Short Pulse Input Signals
With the structure shown in FIG. 19, if for example a short pulse SP occurs in the address signal A0, this short pulse appears unchanged in the output, and the phenomenon occurs that the pulse width of the pulse signal which is output from the NOR gate 8 becomes narrower than the proper pulse width. With regard to this phenomenon, the case in which a short pulse has occurred in the address signal A0 will be explained with reference to the waveform shown in FIG. 24 in concrete terms as an example.
Now, when the address signal A0 is at low level, and a short pulse SP of high level occurs in this address signal A0, this short pulse SP is output through the NAND gate 174 and the NAND gate 175 as the signal S175. In other words, the position of the edge of the short pulse which appears in the signal S175 is determined according to the edge of the short pulse SP in the address signal A0. Here, with proper operation, as shown by the dotted lines in FIG. 24, the falling edge of the signal S175 is determined by receipt of change of the signal S170 which has been delayed by the delay circuit 170. However, since the address signal A0 changes to low level before this, the signal S175 does not respond to the signal S170, and returns to low level in response to the address signal A0. As a result, the pulse width of the signal S175 is narrower than the proper pulse width that is required.
As has been explained above, according to the background art described above, since the pulse width of the one-shot signal is determined using a delay circuit, the pulse width of the one-shot signal easily suffers influences from variations in the delay time of the delay circuit, skew of the input signals, variations in the period of the input signals, short pulses occurring in the input signals, and the like, so that it is not possible to generate the one-shot signal stably.
The present invention was conceived against this type of background, and its objective is to provide a one-shot signal generation circuit with which, by providing, for example, ring oscillators and a plurality of frequency division circuits connected in a cascade, adjustment of the pulse width and countermeasures against variation of the skew of the ATD signals becomes easy, so that it is capable of stably generating a one-shot signal.
The one-shot signal generation circuit according to the first aspect of the present invention comprises a first timing adjustment circuit (for example, a structural element which corresponds to a timing determination section 100 which will be described hereinafter) which is reset by a first edge of a plurality of address transition detection signals (for example, an element which corresponds to an ATD signal output by an address transition detection circuit 3 which will be described hereinafter) which have arrived within a skew period, and takes a second edge of the address transition detection signals as start instant and measures a first predetermined time.
The one-shot signal generation circuit according to the second aspect of the present invention comprises a second timing adjustment circuit (for example, a structural element which corresponds to a timing determination section 110 which will be described hereinafter) which takes a first edge of the initial address transition detection signal among a plurality of address transition detection signals which have arrived within a skew period as start instant and measures a second predetermined time.
The one-shot signal generation circuit according to the third aspect of the present invention comprises, in addition to the structure of the one-shot signal generation circuits according to the first and the second aspects, a generation section (for example, a structural element which corresponds to functions of an LC generation section 14 which will be described hereinafter) which outputs a pulse by taking as start instant the time point at which the second predetermined time has elapsed, and taking as end instant the time point at which the first predetermined time has elapsed for the last address transition detection signal among the plurality of address transition detection signals.
In the one-shot signal generation circuit according to any one of the first through third aspects, each timing adjustment circuit may, for example, be made up by one or more frequency division circuits connected in a cascade. In this case, in each timing adjustment circuit, there may be provided a preparatory circuit (for example, a structural element which corresponds to inverter chains 90 and 150 which will be described hereinafter) which performs fine timing adjustment of the frequency division circuits at the previous stage of the frequency division circuits which are connected in a cascade. Or, in each timing adjustment circuit, there may be provided a preparatory circuit (for example, a structural element which corresponds to a circuit made up from a NAND 111 and a NOR 112 which will be described hereinafter) which performs fine timing adjustment of the frequency division circuits at the next stage of the frequency division circuits which are connected in a cascade. And the preparatory circuit may, for example, be made up of a predetermined number of inverter gates connected in a cascade.
Furthermore, in the one-shot signal generation circuit according to any one of the first through third aspects, each predetermined time may desirably be greater than or equal to the skew period of the address detection signals. Furthermore, for example, a logical sum signal (for example, an element which corresponds to an ATD signal output by an address transition detection circuit 3 which will be described hereinafter) of the plurality of address transition detection signals which have arrived within the skew period may be input to each timing adjustment circuit.
The one-shot signal generation circuit according to the fourth aspect of the present invention generates a one-shot signal in response to change of an input signal, and comprises a signal transition detection section (for example, a structural element which corresponds to an address transition detection circuit 3 which will be described hereinafter) which detects transition of the input signal and generates a pulse signal; and a timing determination section (for example, a structural element which corresponds to timing determination sections 100 and 110 which will be described hereinafter) which detects an edge of the pulse signal, starts a count by taking the edge as a trigger, and determines the timing of edges of the one-shot signal based upon the count value.
In the one-shot signal generation circuit according to the fourth aspect, the timing determination section may desirably determine the edge of the one-shot signal based upon the count value by taking the start edge of the initial pulse signal as a trigger. Furthermore, the timing determination section may, for example, comprise a flip-flop whose stability state is inverted in response to the pulse signal as a trigger, and a counter which starts a count in response to the output signal of the flip-flop as a trigger, and initializes the stability state of the flip-flop based upon the count value of the counter. Furthermore, the counter may, for example, reset the count value based upon the pulse signal. Moreover, for example, the counter may prohibit the resetting of the counter value due to the pulse signal based upon the output signal of the flip-flop.
The one-shot signal generation circuit according to the fifth aspect of the present invention generates a one-shot signal in response to change of an input signal, and comprises: a signal transition detection section which detects transition of the input signal and generates a pulse signal; a timing determination section which, along with detecting a start edge of the pulse signal which is output from the signal transition detection section, starting a count by in response to the start edge as a trigger, and determining the timing of edges of the one-shot signal based upon the count value, and detects an end edge of the pulse signal which is output from the signal transition detection section, starts a count in response to the end edge as a trigger, and determines the timing of an end edge of the one-shot signal based upon the count value; and a signal generation section which generates a one-shot signal having edges whose timing is determined by the timing determination section.
In the one-shot signal generation circuit according to the fourth or fifth aspect, the signal transition detection section, for example, may comprise a plurality of address transition detection circuits which detect transition of a plurality of address signals as the input signal; and a logic gate which combines pulse signals which are respectively output from the plurality of address transition detection circuits into a single signal.
By doing as described above, the present invention can utilize a structure in which the pulse width of the one-shot signal is adjusted not by separate delay circuits, but for example by a single delay circuit and frequency division circuit, and resets the frequency division circuits with the respective address transition detection signals. As a result, it is possible to determine the generation timing and termination timing of the one-shot signal according to a pulse of suitable timing even when the address transition detection signal has been divided into a plurality thereof. Furthermore, it is possible to bring the adjustment points for timing into a single point, so that it is possible to perform reduction of the chip area. Moreover, it is possible to attain the objects without utilizing a circuit with large fan out, since it is possible to obtain the required delay time by frequency dividing the outputs of short delay circuits.